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MON35W82 hardware monitoring ic ? i 2 c interface only features monitoring items - 3 thermal inputs from remote thermistors or 2n3904 npn-type transistors or pentium tm ii (deschutes) thermal diode output - 6 voltage inputs typical for vcore, +3.3v, +12v, -12v, +5v, -5v (optional) - 3 fan speed monitoring inputs - watchdog? comparison of all monitored values - programmable hysteresis and setting points (alarm thresholds) for all monitored items actions enabling - beep tone warning - 2 pwm (pulse width modulation) outputs for fan speed control (mux optional) - total up to 2 sets of fan speed monitoring and controlling. - issues nsmi, novt and ngpo signals to activate system protection - warning signal pop-up in application software general - i 2 c tm serial bus interface - 5 vid input pins for cup vcore identification (for pentium tm ii) - initial power fault beep (for +3.3v, vcore) - intel tm ldcm (dmi driver 2.0) support - acer tm adm (dmi driver 2.0) support - input clock rate optional for 24, 48, and 14.318 mhz - 5v vcc operation package - 24 pin sop general description the MON35W82 is an enhanced version of the mon35w42. the MON35W82 can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for proper operation and stability of a high-end computer system. the MON35W82 provides an i 2 c tm serial bus interface. an 8-bit analog-to-digital converter (adc) is contained inside the MON35W82. the MON35W82 can monitor 6 analog voltage inputs, 3 fan tachometer inputs, and 3 remote temperatures. the remote temperature sensing can be performed by thermistors, 2n3904 npn- type transistors, or directly from intel?s tm deschutes cpu thermal diode output. the MON35W82 also provides: 2 pwm (pulse width modulation) outputs for the fan speed control; beep tone output for warning; nsmi, novt, and ngpo signals for system protection events. with application software such as the intel? ldcm (lan desk client management) the user
2 can read all the monitored parameters of the system from time to time. and a pop-up warning can be activated when the monitored item drifts out of the proper/preset range. also the user can set the upper and lower limits (alarm thresholds) of these monitored parameters and activate programmable and maskable interrupts. an optional beep tone could be used as a warning signal when the monitored parameters are out of the preset range. additionally, 5 vid inputs are provided to read the vid of the cpu (i.e. pentium tm ii) if applicable. this will provide automatic correction of the vcore voltage. the MON35W82 also uniquely provides an optional feature: early stage (before bios is loaded) beep warning. this is to detect if the fatal elements such as vcore or 3.3v voltage fail are present. standard microsystems is a registered trademark and smsc is a trademark of standard microsystems corporation. other product and company names are trademarks or registered trademarks of their respective holders. watchdog is a registered trademark of national semiconductor corporation. key specifications voltage monitoring accuracy 1% (max) monitoring temperature range and accuracy - 40 c to +120 c 3 c (max) supply voltage 5v operating supply current 5 ma typ. adc resolution 8 bits
3 table of contents key specifications ................................ ................................ ................................ ..................... 2 pin description ................................ ................................ ................................ ........................... 6 pin description ................................ ................................ ................................ ........................... 7 functional description ................................ ................................ ................................ ........... 8 general description ................................ ................................ ................................ ............ 8 a ccess i nterface ................................ ................................ ................................ .......................... 8 analog inputs ................................ ................................ ................................ ........................ 12 monitor over 4.096v voltage: ................................ ................................ ................................ .... 13 monitor negative voltage: ................................ ................................ ................................ ......... 14 monitor temperature from thermistor: ................................ ................................ ....................... 15 monitor temperature from pentium ii tm ................................ ................................ ..................... 15 fan s peed c ount and fan s peed c ontrol ................................ ................................ ................. 16 fan speed count ................................ ................................ ................................ ..................... 16 fan speed control ................................ ................................ ................................ ................... 17 t emperature m easurement m achine ................................ ................................ ............................ 18 temperature sensor 2 interrupt mode ................................ ................................ ...................... 19 temperature sensor 1 interrupt mode ................................ ................................ ...................... 20 temperature sensor 1 ................................ ................................ ................................ .............. 21 v oltage and f an n smi mode ................................ ................................ ................................ ........ 22 voltage nsmi mode: ................................ ................................ ................................ ................. 22 fan nsmi mode: ................................ ................................ ................................ ...................... 22 registers and ram ................................ ................................ ................................ .................. 24 c onfiguration r egister - i ndex 40 h ................................ ................................ ............................. 24 i nterrupt s tatus r egister 1 - i ndex 41 h ................................ ................................ ..................... 25 i nterrupt s tatus r egister 2 - i ndex 42 h ................................ ................................ ..................... 25 n smi m ask r egister 1 - i ndex 43 h ................................ ................................ ............................... 26 n smi m ask r egister 2 - i ndex 44 h ................................ ................................ ............................... 27 r eserved r egister ? i ndex 45 h -- 46 h ................................ ................................ ......................... 27 vid/f an d ivisor r egister - i ndex 47 h ................................ ................................ ........................... 28 s erial b us a ddress r egister - i ndex 48 h ................................ ................................ ..................... 28 v alue ram ? i ndex 20 h - 3f h or 60 h - 7f h ................................ ................................ .................. 29 v oltage id (vid4) & d evice id - i ndex 49 h ................................ ................................ ................... 31 t emperature 2 and t emperature 3 s erial b us a ddress r egister --i ndex 4a h ............................... 31 p in c ontrol r egister - i ndex 4b h ................................ ................................ ................................ 32 n irq/ n ovt p roperty s elect - i ndex 4c h ................................ ................................ .................... 33 fan in/out and beep/ n gpo c ontrol r egister - i ndex 4d h ................................ ...................... 34 r egister 50 h ~ 5f h b ank s elect - i ndex 4e h ................................ ................................ ................ 35 smsc v endor id - i ndex 4f h ................................ ................................ ................................ ....... 35 smsc t est r egister -- i ndex 50 h - 55 h (b ank 0) ................................ ................................ ......... 36 beep c ontrol r egister 1-- i ndex 56 h (b ank 0) ................................ ................................ ........... 36
4 beep c ontrol r egister 2-- i ndex 57 h (b ank 0) ................................ ................................ ........... 37 c hip id -- i ndex 58 h (b ank 0) ................................ ................................ ................................ ........ 38 r eserved r egister -- i ndex 59 h (b ank 0) ................................ ................................ ..................... 38 pwmout1 c ontrol r egister -- i ndex 5a h (b ank 0) ................................ ................................ .... 38 pwmout2 c ontrol r egister -- i ndex 5b h (b ank 0) ................................ ................................ .... 39 pwmout1/2 c lock s elect r egister -- i ndex 5c h (b ank 0) ................................ ......................... 39 f an d ivisor c ontrol r egister -- i ndex 5d h (b ank 0) ................................ ................................ .... 40 r eserved r egister -- i ndex 5e h (b ank 0) ................................ ................................ ..................... 41 r eserved r egister -- i ndex 5f h (b ank 0) ................................ ................................ ..................... 41 t emperature s ensor 1 t emperature (h igh b yte ) r egister - i ndex 00 h ................................ ........ 41 t emperature s ensor 1 t emperature (l ow b yte ) r egister - i ndex 00 h ................................ ........ 41 t emperature s ensor 1 c onfiguration r egister - i ndex 01 h ................................ ........................ 42 t emperature s ensor 1 h ysteresis (h igh b yte ) r egister - i ndex 02 h ................................ ........... 43 t emperature s ensor 1 h ysteresis (l ow b yte ) r egister - i ndex 02 h ................................ ............ 43 t emperature s ensor 1 o ver - temperature (h igh b yte ) r egister - i ndex 03 h ............................... 44 t emperature s ensor 1 o ver - temperature (l ow b yte ) r egister - i ndex 03 h ................................ 44 r eserved r egister -- i ndex 50 h --52 h (bank4) ................................ ................................ ............ 45 beep c ontrol r egister 3 -- i ndex 53 h (b ank 4) ................................ ................................ .......... 45 r eserved r egister -- i ndex 54 h --58 h (b ank 4) ................................ ................................ .............. 45 r eal t ime h ardware s tatus r egister i -- i ndex 59 h (b ank 4) ................................ ....................... 45 r eal t ime h ardware s tatus r egister ii -- i ndex 5a h (b ank 4) ................................ ...................... 46 specifications ................................ ................................ ................................ ........................... 47 absolute maximum ratings ................................ ................................ ................................ 47 dc c haracteristics ................................ ................................ ................................ ............. 47 ac characteristics ................................ ................................ ................................ .............. 49 serial bus timing diagram ................................ ................................ ................................ ...... 49 package dimensions ................................ ................................ ................................ ............... 50 80 arkay drive hauppauge, ny 11788 (516) 435-6000 fax (516) 273-3123
5 pin configuration 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 sda 22 21 23 24 vcc vt1/pii1 vref +12vin vcorea +3.3vin -12vin -5vin/vt2/pii2 gnda vid1 fanin1 vid4 beep/ ngpo fanin3/pwmout1 novt nsmi /pwmout2 gndd clkin scl vid2 vid3 fanin2 vid0
6 pin description pin name pin no. type description vid4 1 i n t voltage supply readouts from pentium ii tm . fanin1 2 in ts 0v to 5v amplitude fan tachometer input. fanin2 3 in ts 0v to 5v amplitude fan tachometer input. fanin3 / pwmout1 4 in ts / out 12t 0v to 5v amplitude fan tachometer input. fan speed control (pwm) output. this multi-functional pin is programmable. novt 5 out 12t over temperature shutdown output. beep/ ngp o 6 od 48 beep (default) / general purpose output this multi-functional pin is programmable. vid3 7 i n t voltage supply readouts from pentium ii tm . clkin 8 i n t system clock input. can select 48mhz or 24mhz or 14.318mhz. the default is 24mhz. nsmi / pwmout2 9 od 12 / out 12t system management interrupt (open drain). the default state is disabled. fan speed control (pwm) output. this multi-functional pin is programmable. gndd 10 dground internally connected to all digital circuitry. scl 11 in ts serial bus clock. sda 12 i/o 12ts serial bus bi-directional data. vid2 13 i n t voltage supply readouts from pentium ii tm . vid1 14 i n t voltage supply readouts from pentium ii tm . vid0 15 i n t voltage supply readouts from pentium ii tm . gnda 16 aground internally connected to all analog circuitry. the ground reference for all analog inputs. -5vin / vt2 / pii2 17 ai n 0v to 4.096v fsr analog inputs (default). thermistor 2 terminal input. pentium ii tm thermal 2 diode input. this multi-functional pin is programmable. -12vin 18 ai n 0v to 4.096v fsr analog inputs. +12vin 19 ai n 0v to 4.096v fsr analog inputs. +3.3vin 20 ai n 0v to 4.096v fsr analog inputs. vcorea 21 ai n 0v to 4.096v fsr analog inputs. vref 22 aout reference voltage. vt1 / pii1 23 ai n thermistor 1 terminal input. / pentium ii tm thermal diode 1 input. v cc (+5v) 24 power +5v v cc power. bypass with the parallel combination of 10 m f (electrolytic or tantalum) and 0.1 m f (ceramic) bypass capacitors.
7 pin description i/o 12t ttl level bi-directional pin with 12 ma source-sink capability i/o 12ts ttl level and schmitt trigger out 12 output pin with 12 ma source-sink capability aout output pin(analog) od 12 open-drain output pin with 12 ma sink capability in t ttl level input pin in ts ttl level input pin and schmitt trigger ain input pin(analog)
8 functional description general description the MON35W82 provides 6 analog positive inputs, 3 fan speed monitor inputs, 2 pwm (pulse width modulation) output controls, 2 sets for fan pwm (pulse width modulation) control, 2 thermal inputs from remote thermistors or 2n3904 transistors or penitum tm ii ( deschutes ) thermal diode outputs, a beep function output and a monitor function for the voltage, temperature and fan counters. once the monitor function is initiated, the watchdog monitors each function and stores the value. if the monitored value is not within the limits values, the interrupt status is set and an interrupt can be generated. access interface the MON35W82 provides an i 2 c serial bus to read/write internal registers. there are two serial bus address registers, cr[48h] and cr[4ah] used to read/write all of the internal registers. cr[48h] (default value 0101101) is used to access all registers excluding the bank 1 temperature sensor registers. cr[4ah] (default value 1001001)is used to access the bank 1 temperature sensor registers. the serial bus access timings are shown in the following figures. figure 1 - serial bus write to internal address register followed by the data byte 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by mon35w42 r/nw ack by scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack by stop by master scl sda (continued) 7 8 0 7 8 0 7 8 frame 2 internal index register byte (continued) frame 3 data byte frame 1 serial bus address byte mon35w42 mon35w42
9 figure 2 - serial bus write to internal address register only figure 3 - serial bus read from a register with the internal address register preset to desired location the serial bus timing of the temperature 2 and 3 is shown below: figure 4 - typical 2-byte read from preset pointer location (temp, t os , t hyst ) 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by r/nw ack by scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte stop by master mon35w42 mon35w42 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by master r/nw ack by scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte stop by master mon35w42 0 start by master 0 1 0 1 1 0 1 d7 d1 d0 ack by master r/nw ack by scl sda 7 8 0 7 8 frame 2 msb data byte frame 1 serial bus address byte d7 d1 d0 0 7 stop by master ... ... ... ack by master ... frame 3 lsb data byte mon35w42
10 figure 5 - typical pointer set followed by immediate read for 2-byte register (temp, t os , t hyst ) figure 6 - typical read 1-byte from configuration register with preset pointer 0 start by master d7 d1 d0 ack by master ack by scl sda 7 8 0 7 8 0 frame 4 msb data byte frame 3 serial bus address byte d7 d1 d0 0 7 stop by master ... ... ... no ack by master ... frame 5 lsb data byte 0 start by master 1 0 0 1 a2 a1 a0 r/nw ack by scl sda 7 8 0 frame 1 serial bus address byte 4 d1 d0 ack by frame 2 pointer byte 1 0 0 1 a2 a1 a0 r/nw 0 0 0 0 0 0 mon35w42 mon35w42 mon35w42 mon35w42 0 start by master d7 d2 ack by scl sda 7 8 0 frame 2 data byte frame 1 serial bus address byte d0 7 stop by master no ack by master 1 0 0 1 a2 a1 a0 r/nw d1 d5 d4 d3 d6 8
11 figure 7 - typical pointer set followed by immediate read from configuration register figure 8 - temperature 2/3 configuration register write 0 repea start by master d7 d5 d4 ack by scl (cont..) sda (cont..) 7 8 0 frame 4 msb data byte frame 3 serial bus address byte d2 d1 d0 7 stop by master no ack by master 0 start by master 1 0 0 1 a2 a1 a0 r/nw ack by mon35w42 scl sda 7 8 0 frame 1 serial bus address byte 4 d1 d0 ack by frame 2 pointer byte 1 0 0 1 a2 a1 a0 r/nw ... ... d6 d3 8 7 8 0 0 0 0 0 0 mon35w42 mon35w42 0 ack by scl (cont...) sda (cont...) 7 8 frame 3 configuration data byte 0 0 d4 d3 d2 d1 0 d0 stop by master mon35w42 0 start by master 1 0 0 1 a2 a1 a0 r/nw ack by mon35w42 scl sda 7 8 0 frame 1 serial bus address byte 4 d1 d0 ack by frame 2 pointer byte 0 0 0 0 0 0 0 7 8 mon35w42
12 figure 9 - temperature 2/3 t os and t hyst write analog inputs the analog inputs are normally used to monitor the pc power supplies. the 8-bit adc has a 16mv lsb and supports an input range of 0v to 4.096v. the cpu v-core, 3.3v and battery voltage can be directly connected to these analog inputs. voltages higher than 4.096v must be reduced to the specified input range. an example using external resistors is shown in figure 10. 0 ack by scl (cont...) sda (cont...) 7 8 frame 3 msb data byte 0 start by master 1 0 0 1 a2 a1 a0 r/nw ack by mon35w42 scl sda 7 8 0 frame 1 serial bus address byte 4 d1 d0 ack by frame 2 pointer byte d6 d5 d4 d3 d2 d1 d7 d0 0 7 8 d6 d5 d4 d3 d2 d1 d7 d0 ack by stop by master frame 4 lsb data byte 7 8 0 0 0 0 0 0 mon35w42 mon35w42 mon35w42
13 figure 10 monitor over 4.096v voltage: the input voltage +12vin can be expressed as following equation. 12 1 2 1 2 vin v r r r = + the value of r1 and r2 can be selected as 28k ohms and 10k ohms, respectively, when the input voltage v1 is 12v. the node voltage of +12vin must be less than 4.096v for the maximum input range of the 8-bit adc. the vcc pin (pin 24) is connected to the power supply vcc (+5v). there are two functions in this pin. the first function is to supply internal analog power in the MON35W82 and the second function is to monitor this voltage. the vcc pin is connected to internal serial resistors to monitor the +5v voltage. the value of two serial resistors are 34k ohms and 50k ohms so that the input voltage to the adc is 2.98v which is less than 4.096v of adc maximum input voltage. the voltage equation can be represented as follows. vcore pin 21 +3.3vin 12vin pin 20 pin 19 pin 24 vcc (+5v) n12vin pin 18 r6 r1 v1 n5vin positive input negative input 8-bit adc with 16mv lsb typical thermister connection 10k, 1% r thm vref pin 22 vt1 pin 23 pin 17 positive inputs r5 r7 r8 10k, 25 c **the connections of vt2 is same as vt1 r2 r v3 v4
14 v vcc k k k v in = + @ 50 50 34 2 98 w w w . where vcc is set to 5v. monitor negative voltage: the negative voltage should be connected to two series resistors and a positive voltage vref (equal to 3.6v). in figure 10, voltages v 3 and v4 are two negative voltages, -12v and -5v respectively. the voltage v3 is connected to two series resistors and then is connected to vref which is a positive voltage. the voltage on node n12vin must be between 0v and 4.096v. if r5=232k ohms and r6=56k ohms, the input voltage of node n12vin can be calculated as follows: where vref is equal 3.6v. if the v 3 is equal to -12v then the voltage is equal to 0.567v and the converted hexadecimal data is set to 35h by the 8-bit adc with 16mv- lsb.this monitored value should be converted to the real negative voltage and the express equation is shown as follows. where b is 232k /(232k+56k). if the n2vin is 0.567 then the v3 is approximately equal to -12v. the another negative voltage input v6 (approximate -5v) can also be evaluated by a similar method and the serial resistors can be selected with r 7=120k ohms and r8=56k ohms. the expression equation of v6 with -5v voltage is shown as follows. v n vin vref 6 5 1 = - - g g where the ? is set to 120k/(120k+56k). if the monitored adc value in the n5vin channel is 0.8635, vref=3.6v and the parameter ? is 0.6818 then the negative voltage of v6 can be evaluated to be -5v. n vin vref v v 12 3 3 = + + ( ) ( ) k 232 w k k 232 56 + w w v n vin vref 3 12 1 = - - b b
15 monitor temperature from thermistor: the MON35W82 can connect to three thermistors to measure three different environmental temperatures. the specification of the thermistors are (1) b value is 3435k, (2) resistor value is 10k ohms at 25 c. in figure 10, the thermistor r thm is connected to vt1 and vt1 is connected through a 10k ohm series resistor to vref. monitor temperature from pentium ii tm thermal diode or bipolar transistor 2n3904 the MON35W82 can interface to the pentium ii? ( deschutes) thermal diode interface or a 2n3904 transistor. the circuit connection is shown in figure 11. the pentium ii? d- pin is connected to ground (gnd) and the d+ pin is connected to the pii1 or pii2 pin of the MON35W82. a 30k-ohm resistor must be connected from the piix pin to the vref pin to supply the diode bias current and a bypass capacitor c=3300pf must be added to filter the high frequency noise. if a 2n3904 transistor is used, the base (b) and collector (c) must be tied together to act as a thermal diode. figure 11 2n3904 c e b r=30k, 1% c=3300pf bipolar transistor temperature sensor pentium ii cpu d+ d- therminal diode c=3300pf r=30k, 1% vref piitdx piitdx or MON35W82
16 fan speed count and fan speed control fan speed count inputs are provides for signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and the maximum input voltage can not be over +5.5v. if the input signals from the tachometer outputs are over the vcc, the external trimming circuit should be added to reduce the voltage to obtain the input specification. the normal circuit and trimming circuits are shown in figure 12. determine the fan counter according to: count rpm divisor = 1 35 10 6 . once the fan speed counter has been read from register cr28, cr29 or cr2a, the fan speed can be evaluated by the following equation. rpm count divisor = 1 35 10 6 . the default divisor is 2 and defined at cr47.bit7 :4, cr4b.bit7:6, and bank0 cr5d.bit5:7 which are three bits for the divisor. these provide support for very low speed fans such as power supply fans. the followed table is an example for the relation of divisor, rpm, and count. divisor nominal rpm time per revolution counts 70% rpm time for 70% 1 8800 6.82 ms 153 6160 9.74 ms 2 (default) 4400 13.64 ms 153 3080 19.48 ms 4 2200 27.27 ms 153 1540 38.96 ms 8 1100 54.54 ms 153 770 77.92 ms 16 550 109.08 ms 153 385 155.84 ms 32 275 218.16 ms 153 192 311.68 ms 64 137 436.32 ms 153 96 623.36 ms 128 68 872.64 ms 153 48 1246.72 ms
17 fan speed control the MON35W82 provides four pins for fan pwm speed control. the duty cycle of the pwm can be programmed by an 8-bit register which is defined in bank0 cr5a and cr5b. the default duty cycle is set to 100% , that is, the default 8- bit register is set to ffh. the duty cycle can be represented as follows: the pwm clock frequency also can be program and defined in the bank0.cr5c. the application circuit is shown in figure 13. fan connector fan out +12v gnd pull-up resister 4.7k ohms +5v +12v fan input pin 18/19/20 MON35W82 fan connector fan out +12v gnd pull-up resister 4.7k ohms +12v fan input pin 18/19/20 14k~39k 10k figure 12b - fan with tach pull-up to +12v, or totem-pole output and register attenuator figure 12a - fan with tach pull-up to +5v fan connector fan out +12v gnd pull-up resister > 1k +12v fan input pin 18/19/20 fan connector fan out +12v gnd pull-up resister < 1k or totem-pole output +12v fan input pin 18/19/20 > 1k figure 12d - fan with tach pull-up to +12v, or totem-pole putput and zener clamp figure 12c - fan with tach pull-up to +12v and zener clamp 3.9v zener 3.9v zener diode diode diode diode MON35W82 MON35W82 MON35W82 programmed 8 - bit regist er value 255 duty cycle = (%) 100 %
18 figure 13 temperature measurement machine the temperature data format is 8-bit two?s- complement for sensor 2 and 9-bit two - complement for sensor 1. the 8-bit temperature data can be obtained by reading cr[27h]. the 9-bit temperature data can be obtained by reading the 8 msbs from the bank1 cr[50h] and the lsb from the bank1 cr[51h] bit 7. the format of the temperature data is show in the following table. 8-bit digital output 9-bit digital output temperature 8-bit binary 8-bit hex 9-bit binary 9-bit hex +125 ? c 0111,1101 7dh 0,1111,1010 0fah +25 ? c 0001,1001 19h 0,0011,0010 032h +1 ? c 0000,0001 01h 0,0000,0010 002h +0.5 ? c - - 0,0000,0001 001h +0 ? c 0000,0000 00h 0,0000,0000 000h -0.5 ? c - - 1,1111,1111 1ffh -1 ? c 1111,1111 ffh 1,1111,1110 1ffh -25 ? c 1110,0111 e7h 1,1100,1110 1ceh -55 ? c 1100,1001 c9h 1,1001,0010 192h +12v fan r1 r2 nmos pnp transistor c + - pwm clock input d s g
19 temperature sensor 2 interrupt mode the MON35W82 temperature sensor 2 nsmi interrupt has two modes: (1) comparator interrupt mode setting the t hyst (temperature hysteresis) limit to 127 ? c will set temperature sensor 2 nsmi to the comparator interrupt mode. temperatures which exceed t o (over temperature) limit cause an interrupt and this interrupt will be reset by reading the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t o , the interrupt will occur again when the next conversion has completed. if an interrupt event has occurred by exceeding t o and not reset, the interrupts will not occur again. the interrupts will continue to occur in this manner until the temperature goes below t o . (figure 14a) (2) two-times interrupt mode setting the t hyst lower than t o will set temperature sensor 2 nsmi to the two- times interrupt mode. temperatures exceeding t o causes an interrupt and then the temperature going below t hyst will also cause an interrupt if the previous interrupt has been reset by reading the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will not occur. (figure 14b) t oi * * figure 14a - comparator interrupt mode *interrupt reset when interrupt status registers are read t oi t hyst figure 14b - two-times interrupt mode nsmi nsmi * * * * * t hyst 127'c
20 temperature sensor 1 interrupt mode the MON35W82 temperature sensor 1 nsmi interrupt has three modes (1) comparator interrupt mode temperatures exceeding t o cause an interrupt and this interrupt will be reset by reading the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will occur again when the next conversion has completed. if an interrupt event has occurred by exceeding t o and not reset, the interrupts will not occur again. the interrupt continues to occur in this manner until the temperature goes below t hyst . (figure 15a) (2) two-times interrupt mode the temperature exceeding t o causes an interrupt and then the temperature going below t hyst will also cause an interrupt if the previous interrupt has been reset by reading the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will not occur. (figure 15b) (3 ) one -time interrupt mode the temperature exceeding t o causes an interrupt and then the temperature going below t hyst will not cause an interrupt. once an interrupt event has occurred by exceeding t o , then going below t hyst , an interrupt will not occur again until the temperature exceeds t o . (figure 15c) t oi t hyst * * * *interrupt reset when interrupt status registers are read t oi t hyst nsmi nsmi * * * * * figure 15a - comparator interrupt mode figure 15b - two-times interrupt mode
21 temperature sensor 1 over-temperature ( novt) modes (1) comparator mode: setting bank1 cr[52h] bit 2 to 0 will set novt signal to comparator mode. the temperature exceeding t o causes the novt output activated until the temperature is less than t hyst . (figure 16) (2) interrupt mode: setting bank1 cr[52h] bit 2 to 1 will set novt signal to interrupt mode. setting temperature exceeding t o causes the novt output activated indefinitely until reset by reading temperature sensor 2 or sensor 3 registers. the temperature exceeding t o , then novt reset, and then temperature going below t hyst will also cause the novt activated indefinitely until reset by reading temperature sensor 2 or sensor 3 registers. once the novt is activated by exceeding t o , then reset, if the temperature remains above t hyst , the novt will not be activated again.( figure 16) *interrupt reset when interrupt status registers are read t oi t hyst figure 15c - one-time interrupt mode nsmi * *
22 figure 16 ? over-temperature response diagram voltage and fan nsmi mode voltage nsmi mode: nsmi interrupt for voltage monitoring is two-times interrupt mode. voltage exceeding the high limit or going below the low limit will cause an interrupt if the previous interrupt has been reset by reading the interrupt status register. (figure 17) fan nsmi mode: nsmi interrupt for fan monitoring is two- times interrupt mode. fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading the interrupt status register. (figure 17) t hyst * * * *interrupt reset when temperature 2/3 is read novt novt * (comparator mode; default) (interrupt mode) to
23 * * * figure 17a - voltage nsmi mode *interrupt reset when interrupt status registers are read figure 17b - fan nsmi mode nsmi * high limit low limit * nsmi * fan count limit
24 registers and ram configuration register - index 40h register location: 40 h power on default value 00000001 binary attribute: read/write size: 8 bits bit 7: a one restores power on default values t o all registers except the serial bus address register. this bit clears itself since the power on default is zero. bit 6: a one drives a zero on beep/ ngpo pin. bit 5: reserved bit 4: reserved bit 3: a one disables the nsmi output without affecting the contents of the interrupt status registers. the device will stop monitoring. it will resume monitoring when this bit is cleared. bit 2: reserved bit 1: a one enables the nsmi interrupt output. bit 0: a one enables startup of monitoring operations, a zero puts the part in standby mode. note: the outputs of interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike " int_clear'' bit. 7 6 5 4 3 2 1 0 start nsmienable reserved int_clear reserved reserved beep/ngpo initialization
25 interrupt status register 1 - index 41h register location: 41 h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 vcore reserved +3.3vin +5vin temp2 temp1 fan1 fan2 bit 7: a one indicates the fan count limit of fan2 has been exceeded. bit 6: a one indicates the fan count limit of fan1 has been exceeded. bit 5: a one indicates a high limit of vt1 has been exceeded from temperature sensor. bit 4: a one indicates a high limit of vt2 has been exceeded from temperature sensor. bit 3: a one indicates a high or low limit of +5vin has been exceeded. bit 2: a one indicates a high or low limit of +3.3vin has been exceeded. bit 1: reserved. bit 0: a one indicates a high or low limit of vcore has been exceeded. interrupt status register 2 - index 42h register location: 42 h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 +12vin -12vin -5vin fan3 reserved reserved reserved reserved bit 7-4: reserved.this bit should be set to 0. bit 3: a one indicates the fan count limit of fan3 has been exceeded. bit 2: a one indicates a high or low limit of -5vin has been exceeded. bit 1: a one indicates a high or low limit of -12vin has been exceeded. bit 0: a one indicates a high or low limit of +12vin has been exceeded.
26 nsmi mask register 1 - index 43h register location: 43 h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 vcore reserved +3.3vin +5vin temp2 temp1 fan1 fan2 bit 7-0: a one disables the corresponding interrupt status bit for nsmi interrupt.
27 nsmi mask register 2 - index 44h register location: 44 h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 +12vin -12vin -5vin fan3 reserved reserved reserved reserved bit 7-4: reserved. this bit should be set to 0. bit 3-0: a one disables the corresponding interrupt status bit for nsmi interrupt. reserved register ? ? index 45h-- 46h
28 vid/fan divisor register - index 47h register location: 47 h power on default value <7:4> is 0101, <3:0> is mapped to vid<3:0> attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 vid0 vid1 vid2 vid3 fan1div_b0 fan1div_b1 fan2div_b0 fan2div_b1 bit 7-6: fan2 speed control. bit 5-4: fan1 speed control. bit 3-0: the vid <3:0> inputs note: please refer to bank0 cr[5dh] , fan divisor table. serial bus address register - index 48h register location: 48 h power on default value serial bus address <6:0> = 0101101 and <7> = 0 binary size: 8 bits 7 6 5 4 3 2 1 0 serial bus address reserved bit 7: read onl y - reserved. bit 6-0: read/write - serial bus address <6:0>.
29 value ram ? ? index 20h- 3fh or 60h - 7fh index description 20h or 60h vcore reading 21h or 61h reserved 22h or 62h +3.3vin reading 23h or 63h +5vin reading 24h or 64h +12vin reading 25h or 65h -12vin reading 26h or 66h -5vin reading 27h or 67h temperature sensor 2 (vt2) reading 28h or 68h fan1 reading note: this location stores the number of counts of the internal clock per revolution. 29h or 69h fan2 reading note: this location stores the number of counts of the internal clock per revolution. 2ah or 6ah fan3 reading note: this location stores the number of counts of the internal clock per revolution. 2bh or 6bh vcore high limit, default value is defined by vcore voltage +0.2v. 2ch or 6ch vcore low limit, default value is defined by vcore voltage - 0.2v. 2dh or 6dh reserved 2eh or 6eh reserved 2fh or 6fh +3.3vin high limit 30h or 70h +3.3vin low limit 31h or 71h +5vin high limit 32h or 72h +5vin low limit
30 value ram ? ? index 20h- 3fh or 60h - 7fh, continued address a6-a0 description 33h or 73h +12vin high limit 34h or 74h +12vin low limit 35h or 75h -12vin high limit 36h or 76h -12vin low limit 37h or 77h -5vin high limit 38h or 78h -5vin low limit 39h or 79h temperature sensor 2 (vt2) high limit 3ah or 7ah temperature sensor 2 (vt2) hysteresis limit 3bh or 7bh fan1 fan count limit note: it is the number of counts of the internal clock for the low limit of the fan speed. 3ch or 7ch fan2 fan count limit note: it is the number of counts of the internal clock for the low limit of the fan speed. 3dh or 7dh fan3 fan count limit note: it is the number of counts of the internal clock for the low limit of the fan speed. 3e- 3fh or 7e-7fh reserved setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits.
31 voltage id (vid4) & device id - index 49h register location: 49 h power on default value <7:1> is 000,0001b <0> is mapped to vid <4> size: 8 bits 7 6 5 4 3 2 1 0 did<6:0> vid4 bit 7-1: read only - device id<6:0> bit 0 : read/write - the vid4 inputs. temperature 2 and temperature 3 serial bus address register--index 4ah register location: 4a h power on default value <7:0> = 0000,0001 binary. reset by mr attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 i2caddr2 i2caddr2 i2caddr2 dis_t2 reserved reserved reserved reserved bit 7-4 : reserved bit 3: set to 1, disable temperature sensor 1 and can not access any data f rom temperature sensor 1. bit 2-0: temperature 2 serial bus address. the serial bus address is 1001xxx. where xxx are defined in these bits.
32 pin control register - index 4bh register location: 4b h power on default value <7:0> 44h. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved clkinsel clkinsel adcovsel adcovsel fan3div_b0 fan3div_b1 bit 7-6:fan3 speed divisor. please refer to bank0 cr[5dh] , fan divisor table. bit 5-4: select a/d converter clock input. <5:4> = 00 - default. adc clock select 22.5 khz <5:4> = 01 - adc clock select 5.6 khz . (22.5k/4) <5:4> = 10 - adc clock select 1.4 khz . (22.5k/16) <5:4> = 11 - adc clock select 0.35 khz . (22.5k/64) bit 3-2: clock input select. <3:2> = 00 - pin 3 (clkin) select 14.318mhz clock. <3:2> = 01 - default. pin 3 (clkin) select 24mhz clock. <3:2> = 10 - pin 3 (clkin) select 48mhz clock . <3:2> = 11 - reserved. pin3 no clock input. bit 1-0: reserved. user defined.
33 nirq/ novt property select - index 4ch register location: 4c h power on default value <7:0> --0000,0001. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved ovtpol dis_ovt reserved en_one_intmode t1_intmode pwm2sel bit 7: set to 1 , select pin 9 nsmi/pwmout2 as pwm output. set to 0, select pin 9 as nsmi output. bit6: set to 1, the nsmi output type of temperature sensor 1 is set to comparator interrupt mode. set to 0, the nsmi output type is set to interrupt mode (defined by cr[4ch] bit 5). bit 5: set to 1, the nsmi output type of temperature sensor 1 is set to one-time interrupt mode. set to 0, the nsmi output type of temperature sensor 1 is set to two-times interrupt mode. bit 4 : reserved. user defined. bit 3: disable temperature sensor 1 over-temperature (ovt) output if set to 1. default 0 , enable ovt1 output through pin novt. bit 2: over-temperature polarity. write 1, novt active high. write 0, novt active low. default 0. bit 1-0: reserved. user defined.
34 fan in/out and beep/ ngpo control register - index 4dh register location: 4d h power on default value <7:0> 0001,0101. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 faninc1 fanopv1 faninc2 fanopv2 faninc3 fanopv3 gposel dis_abn bit 7: disable power-on abnormal voltage monitoring including v-core a and +3.3v. if these voltages exceed the limit value, the beep pin (open drain) will drive a 300hz or 600hz frequency signal. write 1 , the frequency will be disable. default 0. after power on, the system should set this bit to 1 in order to disable beep. bit 6: beep/ ngpo pin function select. write 1 select ngpo function. set 0, select beep function. this bit defaults to 0. bit 5: fan 3 output value if faninc3 is set to 0. if this bit is a 1, then pin 4 always generates a logic high signal. if this bit is a 0, pin 4 always generates logic low signal. this bit defaults to 0. bit 4: fan 3 input control. set to 1(default), pin 4 acts as fan clock input. set to 0, pin 4 acts as fan control signal and the output value of fan control is set by register bit 5. this output pin can connect to power pmos gate to control fan on/off. bit 3: fan 2 output value if faninc2 is set to 0. if this bit i s 1, then pin 3 always generates a logic high signal. if 0 (default), pin 3 always generates a logic low signal. bit 2: fan 2 input control. set to 1(default), pin 3 acts as fan clock input. set to 0, pin 3 acts as fan control signal and the output value of fan control is set by this register bit 3. this output pin can connect to power nmos gate to control fan on/off. bit 1: fan 1 output value if faninc1 is sets to 0. if 1, then pin 2 always generates a logic high signal. if 0(default), pin 2 always generates a logic low signal. bit 0: fan 1 input control. set to 1(default), pin 2 acts as fan clock input. set to 0, pin 2 acts as fan control signal and the output value of fan control is set by register bit 1. this output pin can connect to power pmos gate to control fan on/off.
35 register 50h ~ 5fh bank select - index 4eh register location: 4e h power on default value <6:3> = reserved, <7> = 1, <2:0> = 0. reset by mr attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 banksel0 banksel1 banksel2 reserved reserved reserved reserved hbacs bit 7: hbacs- hi gh byte access. set to 1(default), access register 4fh high byte register. set to 0, access register 4fh low byte register. bit 6-3: reserved. this bit should be set to 0. bit 2-0: index ports 0x50~0x5f bank select. smsc vendor id - index 4fh register location: 4f h power on default value <15:0> = 5ca3h attribute: read only size: 16 bits 15 8 7 0 vidh vidl bit 15-8: vendor id high byte if cr4e.bit7=1. default 5ch. bit 7-0: vendor id low byte if cr4e.bit7=0. default a3h.
36 smsc test register -- index 50h - 55h (bank 0) beep control register 1-- index 56h ( bank 0 ) register location: 56 h power on default value <7:0> 0000,0000. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_vc_bp reserved en_v33_bp en_v5_bp en_t2_bp en_t1_bp en_fan1_bp en_fan2_bp bit 7: enable beep output from fan 2 if the monitor value exceeds the limit value. if set to 1(default) enable beep output. bit 6: enable beep output from fan 1 if the monitor value exceeds the limit value. if set to 1(default), enable beep output. bit 5: enable be ep output from temperature sensor 1 if the monitor value exceeds the limit value. if set to 1, enable beep output. default is 0. bit 4: enable beep output for temperature sensor 2 if the monitor value exceed the limit value. if set to 1, enable beep output. default is 0 bit 3: enable beep output from vdd (+5v), if set to 1, enable beep output if the monitor value exceeds the limits value. default is 0, disable beep output. bit 2: enable beep output from +3.3v. if set to 1(default), enable beep output. bit 1: reserved. bit 0: enable beep output from vcore if the monitor value exceeds the limits value. if set to 1(default), enable beep output.
37 beep control register 2-- index 57h ( bank 0 ) register location: 57 h power on default value <7:0> 1000-0000. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_v12_bp en_nv12_bp en_nv5_bp en_fan3_bp reserved reserved reserved en_gbp bit 7: enable global beep. if set to 1, enable global beep output. default 1. if set to 0, disable all beep outputs. bit 6-4: reserved. bit 3: enable beep outp ut from fan 3 if the monitor value exceeds the limit value. if set to 1, enable beep output. default 0. bit 2: enable beep output from -5v, if set to 1, enable beep output if the monitor value exceeds the limits value. default 0, disable beep output. bit 1: enable beep output from -12v, if set to 1, enable beep output if the monitor value exceeds the limits value. default 0, disable beep output. bit 0: enable beep output from +12v, if set to 1, enable beep output if the monitor value exceed the limits value. default 0, disable beep output.
38 chip id -- index 58h ( bank 0 ) register location: 58 h power on default value <7:0> 0100-0000. reset by mr. attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 chipid bit 7: smsc chip id number. read this register will return 40h. reserved register -- index 59h ( bank 0 ) pwmout1 control register -- index 5ah ( bank 0 ) register location: 5a h power on default value: <7:0> 1111-1111. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 pwm1_duty bit 7: pwmout1 duty cycle control if ?ff?, duty cycle is 100%, if ?00?, duty cycle is 0%.
39 pwmout2 control register -- index 5bh ( bank 0 ) register location: 5b h power on default value: <7:0> 1111-1111. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 pwm2_duty bit 7: pwmout2 duty cycle control if ?ff?, duty cycle is 100%, if ?00?, duty cycle is 0%. pwmout1/2 clock select register -- index 5ch ( bank 0 ) register location: 5c h power on default value <7:0> 0001-0001. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 pwm2clksel pwm2clksel pwm2clksel en_fanpwm1 pwm1clksel pwm1clksel pwm1clksel reserved bit 7: reserved bit 6-4: pwmout1 clock selection. the clock-defined frequency is same as pwmout2 clock selection.
40 bit 3: set to 1. enable pwmout1 pwm control bit 2-0: pwmout2 clock selection. <2:0> = 000: 46.87khz <2:0> = 001: 23.43khz (default) <2:0> = 010: 11.72khz <2:0> = 011 : 5.85khz <2:0> = 100 : 2.93khz fan divisor control register -- index 5dh ( bank 0 ) register location: 5d h power on default value <7:0> 0000-0000. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved fandiv1_b2 fandiv2_b2 fandiv3_b2 bit 7: fan3 divisor bit 2. bit 6: fan2 divisor bit 2. bit 5: fan1 divisor bit 2. bit 4-0: reserved fan divisor table bit 2 bit 1 bit 0 fan divisor bit 2 bit 1 bit 0 fan divisor 0 0 0 1 1 0 0 16 0 0 1 2 1 0 1 32 0 1 0 4 1 1 0 64 0 1 1 8 1 1 1 128
41 reserved register -- index 5eh ( bank 0 ) reserved register -- index 5fh ( bank 0 ) temperature sensor 1 temperature (high byte) register - index 00h register location: 00 h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp2<8:1> bit 7-0: temperature <8:1> of sensor 2, bit 7 is msb. temperature sensor 1 temperature (low byte) register - index 00h register location: 00 h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp2<0> reserved bit 7: temperature <0> of sensor2, lsb. bit 6-0: reserved. this bit should be set to 0.
42 temperature sensor 1 configuration register - index 01h register location: 01 h power on default value <7:0> = 0x00 size: 8 bits 7 6 5 4 3 2 1 0 stop2 intmod reserved fault fault reserved reserved reserved bit 7-5: read - reserved. this bit should be set to 0. bit 4-3: read/write - number of faults to detect before setting novt output to avoid false tripping due to noise. bit 2: read - reser ved. this bit should be set to 0. bit 1: read/write - novt interrupt mode select. if set to 0(default), compared mode. if set to 1, interrupt mode will be selected. bit 0: read/write - when set to 1 the sensor will stop monitoring.
43 temperature sensor 1 hysteresis (high byte) register - index 02h register location: 02 h power on default value <7:0> = 0x4b attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 thyst2<8:1> bit 7-0: temperature hysteresis bit 8-1, bit 7 is msb. the temperature default is 75 degree c. temperature sensor 1 hysteresis (low byte) register - index 02h register location: 02 h power on default value <7:0> = 0x0 attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 thyst2<0> reserved bit 7: temperature hysteresis bit 0, lsb. bit 6-0: reserved. this bit should be set to 0.
44 temperature sensor 1 over-temperature (high byte) register - index 03h register location: 03 h power on default value <7:0> = 0x50 attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 tovf2<8:1> bit 7-0: over-temperature bit 8-1, bit 7 is msb. the temperature default 80 degree c. temperature sensor 1 over-temperature (low byte) register - index 03h register location: 03 h power on default value <7:0> = 0x0 size: 8 bits 7 6 5 4 3 2 1 0 tovf2<0> reserved bit 7: read/write - over-temperature bit 0, lsb. bit 6-0: read only - reserved. this bit should be set to 0.
45 reserved register -- index 50h--52h (bank4) beep control register 3 -- index 53h ( bank 4 ) register location: 53 h power on default value <7:0> 0000,0000. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved en_user_bp reserved reserved bit 7-6: reserved. bit 5: user define beep output function. if set to 1, the beep is always active. if set to 0, this function is inactive. (default 0) bit 4-0: reserved. reserved register -- index 54h--58h ( bank 4 ) real time hardware status register i -- index 59h ( bank 4 ) register location: 59 h power on default value <7:0> 0000,0000. reset by mr. attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 vcore_sts reserved +3.3vin_sts +5vin_sts temp2_sts temp1_sts fan1_sts fan2_sts
46 bit 7: fan 2 status. if 1, the fan speed counter is over the limit value. if 0, the fan speed counter is in the limit range. bit 6: fan 1 status. if 1, the fan speed counter is over the limit value. if 0, the fan speed counter is in the limit range. bit 5: temperature sensor 1 status. if 1, the voltage of temperature sensor is over the limit value. if 0, the voltage of temperature sensor is in the limit range. bit 4: temperature sensor 2 status. if 1 , the voltage of temperature sensor is over the limit value. if 0, the voltage of temperature sensor is in the limit range. bit 3: +5v voltage status. if 1, the voltage of +5v is over the limit value. if 0, the voltage of +5v is in the limit range. bit 2: +3.3v voltage status. if 1, the voltage of +3.3v is over the limit value. if 0, the voltage of +3.3v is in the limit range. bit 1: reserved. bit 0: vcore voltage status. if 1, the voltage of vcore is over the limit value. if 0, the voltage of vcore is in the limit range. real time hardware status register ii -- index 5ah ( bank 4 ) register location: 5a h power on default value <7:0> 0000,0000. reset by mr. attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 +12vin_sts -12vin_sts -5vin_sts fan3_sts reserved reserved reserved reserved bit 7-4: reserved bit 3: fan3 voltage status. if 1, the fan speed counter is over the limit value. if 0, the fan speed counter is during the limit range. bit 2: -5v voltage status. if 1, the voltage of -5v is over the limit value. if 0, the voltage of -5v is during the limit range. bit 1: -12v voltage status. if 1, the voltage of -12v is over the limit value. if 0, the voltage of -12v is during the limit range. bit 0: +12v voltage status. if 1, the voltage of +12v is over the limit value. if 0, the voltage of +12v is in the limit range.
47 specifications absolute maximum ratings parameter rating unit power supply voltage -0.5 to 7.0 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (ta = 0 c to 70 c, vdd = 5v 10%, vss = 0v) parameter sym. min. typ. max. unit conditions i/o 12t - ttl level bi-directional pin with source-sink capability of 12 ma input low voltage vil 0.8 v input high voltage vih 2.0 v output low voltage vol 0.4 v iol = 12 ma output high voltage voh 2.4 v ioh = - 12 ma input high leakage ilih +10 m a vin = vdd input low leakage ilil -10 m a vin = 0v i/o 12ts - ttl level bi-directional pin with source-sink capability of 12 ma and schmitt- trigger level input input low threshold voltage vt- 0.5 0.8 1.1 v vdd = 5 v input high threshold voltage vt+ 1.6 2.0 2.4 v vdd = 5 v hysteresis vth 0.5 1.2 v vdd = 5 v output low voltage vol 0.4 v iol = 12 ma output high voltage voh 2.4 v ioh = - 12 ma input high leakage ilih +10 m a vin = vdd input low leakage ilil -10 m a vin = 0v out 12t - ttl level output pin with source-sink capability of 12 ma output low voltage vol 0.4 v iol = 12 ma output high voltage voh 2.4 v ioh = -12 ma od 8 - open-drain output pin with sink capability of 8 ma output low voltage vol 0.4 v iol = 8 ma od 12 - open-drain output pin with sink capability of 12 ma output low voltage vol 0.4 v iol = 12 ma od 48 - open-drain output pin with sink capability of 48 ma output low voltage vol 0.4 v iol = 48 ma in t - ttl level input pin input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +10 m a vin = vdd
48 parameter sym. min. typ. max. unit conditions input low leakage ilil -10 m a vin = 0 v in ts - ttl level schmitt-triggered input pin input low threshold voltage vt- 0.5 0.8 1.1 v vdd = 5 v input high threshold voltage vt+ 1.6 2.0 2.4 v vdd = 5 v hysteresis vth 0.5 1.2 v vdd = 5 v input high leakage ilih +10 m a vin = vdd input low leakage ilil -10 m a vin = 0 v
49 ac characteristics serial bus timing diagram valid data scl sda in sda out t hd;sda t scl t hd;dat t su;sto t su;dat serial bus timing diagram serial bus timing parameter symbol min. max. unit scl clock period t - scl 10 us start condition hold time t hd;sda 4.7 us stop condition setup-up time t su;sto 4.7 us data to scl setup time t su;dat 120 ns data to scl hold time t hd;dat 5 ns scl and sda rise time t r 1.0 us scl and sda fall time t f 300 ns
package dimensions (24 pin sop) ? 199 9 standard microsystems corporation (smsc) circuit diagrams utilizing smsc products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. the information has been carefully checked and is believed to be entirely reliable. however, no responsibility is assumed for inaccuracies. furthermore, such information does not convey to the purchaser of the semiconduc tor devices described any licenses under the patent rights of smsc or others. smsc reserves the right to make changes at any time in order to improve design and supply the best product possible. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. MON35W82 rev. 1/ 12 /1999 l o c 0.25 gauge plane e h a1 a e b d seating plane y e 1 24 13 12 7.60 0.32 0.51 0.30 e c b a1 7.40 0.23 0.33 0.10 0.299 0.013 0.020 0.012 0.291 0.009 0.013 0.004 max. dimension in mm 2.65 a symbol min. 2.35 dimension in inch 0.104 min. 0.093 max. control demensions are in milmeters . 1.27 0.10 10.65 l q q y h 0 8 0.40 10.00 e 1.27 bsc 0.050 0.004 0.419 0 0.016 0.394 8 0.050 bsc e d 15.20 15.60 0.598 0.614

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